View IP4773CZ14_4547706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IP4773CZ14
VGA Interface with integrated buffer, ESD protection and termination resistor
Rev. 01 -- 24 February 2009 Product data sheet
1. General description
The IP4773CZ14 is a VGA or DVI-I interface intended to be connected between a video transmitter such as a PC graphics card and a VGA or DVI-I receiver, such as a PC monitor. The IP4773CZ14 has ESD protection for the DDC lines, ESD protection plus buffering for the h-sync and v-sync lines and high-level ESD protection diodes for the R, G, B video signal lines. The synchronizing signals are buffered by non-inverting buffers which can accept TTL-level input. The buffers convert TTL-level input to CMOS-level output which swings between VCC(SYNC) and GND. An external termination resistor can be added to achieve the desired termination, which is typically required for the h-sync and v-sync lines of the video interface. The IP4773CZ14 has a typical output resistance (RO) of 10 .
2. Features
I Integrated high-level ESD protection, buffering, sync-signal impedance matching I All pin connections have integrated rail-to-rail clamping diodes providing downstream ESD protection of 8 kV according to IEC 61000-4-2, level 4 I Drivers for h-sync and v-sync lines I Line capacitance < 4 pF per channel
3. Applications
Buffer and terminating channels, reduce EMI and RFI, and provide downstream ESD protection for: I VGA interfaces including DDC channels I Desktop and notebook PCs, LCD TVs and PC monitors I Graphics cards I Set-top boxes I Game consoles I DVD players
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
4. Ordering information
Table 1. Ordering information Package Name IP4773CZ14 SSOP14 Description plastic shrink small outline package; 14 leads; body width 5.3 mm Version SOT337-1 Type number
5. Functional diagram
VCC(VIDEO)
VIDEO_1 VIDEO_2 VIDEO_3
GND
BYP
VCC(SYNC)
SYNC_OUT2
DDC_IN1 DDC_IN2 SYNC_IN1 SYNC_IN2
SYNC_OUT1
001aai172
Fig 1.
Functional diagram
6. Pinning information
6.1 Pinning
IP4773CZ14
VIDEO_1 VIDEO_2 VIDEO_3 SYNC_IN1 SYNC_IN2 DDC_IN1 DDC_IN2 1 2 3 4 5 6 7
001aai171
14 VCC(VIDEO) 13 GND 12 SYNC_OUT1 11 SYNC_OUT2 10 GND 9 8 VCC(SYNC) BYP
Fig 2.
Pin configuration
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
2 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
6.2 Pin description
Table 2. Symbol VIDEO_1 VIDEO_2 VIDEO_3 SYNC_IN1 SYNC_IN2 DDC_IN1 DDC_IN2 BYP VCC(SYNC) GND SYNC_OUT2 SYNC_OUT1 GND VCC(VIDEO) Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description ESD protection for video channel 1 ESD protection for video channel 2 ESD protection for video channel 3 sync signal input 1 sync signal input 2 DDC signal input 1 DDC signal input 2 for connecting a 100 nF bypass capacitor to increase ESD clamping performance of the DDC outputs supply voltage for sync buffer ground sync signal output 2 sync signal output 1 ground supply voltage for video protection circuit
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(VIDEO) VCC(SYNC) VI Parameter video supply voltage synchronization supply voltage input voltage pins VIDEO_1, VIDEO_2, VIDEO_3 pins SYNC_IN1, SYNC_IN2, DDC_IN1, DDC_IN2 VESD Ptot electrostatic discharge voltage total power dissipation IEC 61000-4-2, level 4, contact Tamb = 25 C; fsync = 100 kHz, CL = 6 nF, RL = 10 k
[1]
Conditions
Min GND - 0.5 3.0 GND - 0.5 GND - 0.5
Max 5.5 5.5 VCC(VIDEO) VCC(SYNC)
Unit V V V V
-8 -
+8 50
kV mW
Tstg
[1]
storage temperature
-55
+125
C
Pins BYP, VCC(VIDEO) and VCC(SYNC) must be bypassed to GND via a low-impedance ground plane with 100 nF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between pins (VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2) and GND.
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
3 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
8. Characteristics
Table 4. Characteristics Tamb = 25 C unless otherwise specified. Symbol ICC(VIDEO) Cch II VFd DDC Cch II VFd Sync buffer VCC(SYNC) ICC(SYNC) Cch II VFd VIH VIL VOH VOL RO tPLH tPHL tr(o) tf(o) synchronization supply voltage supply current on pin VCC(SYNC) channel capacitance input current diode forward voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage output resistance LOW to HIGH propagation delay HIGH to LOW propagation delay output rise time output fall time VCC(SYNC) = 5.0 V; CL = 50 pF; tr(i) and tf(i) 5 ns VCC(SYNC) = 5.0 V; CL = 50 pF; tr(i) and tf(i) 5 ns VCC(SYNC) = 5.0 V; CL = 50 pF; tr(i) and tf(i) 5 ns VCC(SYNC) = 5.0 V; CL = 50 pF; tr(i) and tf(i) 5 ns VCC(SYNC) = 5.0 V; static input signals VCC(SYNC) = 5.0 V; f = 1 MHz; Vbias = 1.65 V VCC(SYNC) = 5.0 V; VI = VCC(SYNC) or GND IF = 1 mA VCC(SYNC) = 5.0 V VCC(SYNC) = 5.0 V VCC(SYNC) = 5.0 V; IOH = 24 mA VCC(SYNC) = 5.0 V; IOL = 24 mA
[3] [3] [3] [3] [3] [1] [2]
Parameter supply current on pin VCC(VIDEO) channel capacitance input current diode forward voltage channel capacitance input current diode forward voltage
Conditions VCC(VIDEO) = 5.0 V; static input signals VCC(VIDEO) = 5.0 V; f = 1 MHz; VI = 2.5 V (p-p); Vbias = 2.5 V VCC(VIDEO) = 5.0 V; VI = VCC(VIDEO) or GND IF = 1 mA f = 1 MHz; VI = 2.5 V (p-p); Vbias = 2.5 V VI = 5.0 V IF =1 mA
[1] [1]
Min 3.0 2.0 2.0 -
Typ 0.7 0.7 5.0 0.7 10 4 4
Max 10 4 1 4 1 5.5 10 4 1 0.6 0.8 12 12 -
Unit A pF A V pF A V V A pF A V V V V V ns ns ns ns
Analog video (RGB)
[1]
[1]
[1] [2] [3]
Guaranteed by design and characterization. Sync buffer outputs unloaded. Applies only to the Sync buffer; note that RO = Rbuffer.
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
4 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
9. Application information
9.1 Connections
The IP4773CZ14 should be placed as close as possible to the VGA or DVI-I interface connector. The ESD-protected channels on pins VIDEO_1, VIDEO_2 and VIDEO_3 can be connected in any order to R, G, B signals. The sync buffers are equivalent and can be connected to either h-sync or v-sync signals.
RED GREEN BLUE
FILTER FILTER FILTER
VIDEO_1 VIDEO_2 VIDEO_3
VCC(VIDEO) BYP
VCC_DAC
VSYNC
SYNC_IN1
SYNC_OUT1
VSYNC_OUT
IP4773CZ14
HSYNC SYNC_IN2 SYNC_OUT2 HSYNC_OUT
DDC_Clock DDC_Data
DDC_IN1 DDC_IN2 VCC(SYNC) GND VCC_5V
SYNC_ GND
BLUE GREEN RED RGB GND
DDC_Clock
DDC_Data
001aai173
Fig 3.
Transmitter application
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
5 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
RED GREEN BLUE
VIDEO_1 VIDEO_2 VIDEO_3
VCC(VIDEO) BYP
VCC_DAC
HSYNC
SYNC_IN1
SYNC_OUT1
HSYNC_OUT
IP4773CZ14
VSYNC SYNC_IN2 SYNC_OUT2 VSYNC_OUT
DDC_Clock DDC_Data
DDC_IN1 DDC_IN2 VCC(SYNC) GND VCC_5V
SYNC_ GND
BLUE GREEN RED RGB GND
DDC_Clock
DDC_Data
001aai174
Fig 4.
Receiver application
The receiver application simplifies VGA input circuit applications.
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
6 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
10. Package outline
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
D
E
A X
c y HE vM A
Z 14 8
Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 5.
IP4773CZ14_1
Package outline SOT337-1 (SSOP14)
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
7 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
11. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
11.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
11.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
11.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
IP4773CZ14_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
8 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
11.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 6) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 5 and 6
Table 5. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 6. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 6.
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
9 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 6.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
12. Abbreviations
Table 7. Acronym DDC DVI-I EMI ESD RGB RFI TTL VGA Abbreviations Description Display Data Channel Digital Visual Interface Integrated (Analog and Digital) ElectroMagnetic Interference ElectroStatic Discharge Red, Green, Blue Radio Frequency Interference Transistor-Transistor Logic Video Graphics Array
13. Revision history
Table 8. Revision history Release date 20090224 Data sheet status Product data sheet Change notice Supersedes Document ID IP4773CZ14_1
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
10 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
IP4773CZ14_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 24 February 2009
11 of 12
NXP Semiconductors
IP4773CZ14
VGA interface with ESD protection
16. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 9.1 10 11 11.1 11.2 11.3 11.4 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information. . . . . . . . . . . . . . . . . . . 5 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Soldering of SMD packages . . . . . . . . . . . . . . . 8 Introduction to soldering . . . . . . . . . . . . . . . . . . 8 Wave and reflow soldering . . . . . . . . . . . . . . . . 8 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 February 2009 Document identifier: IP4773CZ14_1

▲Up To Search▲

Price & Availability of IP4773CZ14

	To Download IP4773CZ14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .